The confirmation of the logic state of a signal means the assurance that this signal has been in this logic state for at least a certain time. The aim is to eliminate all bounce phenomena and other interference phenomena, by filtering pulses that are too short with respect to the average frequency of the observed logic transitions for the signal in question. In this manner, the application will not see these too short pulses and will therefore not be disrupted or induced into error by incorrect information.
Such a confirmation mechanism is notably useful in application systems comprising sensitive functions such as security functions, the processing processes of which are based on the state of logic signals which may be, for example, signals supplied by control members or signals supplied by sensors, reporting the state of certain hardware or of software processes.
In case of input signals coded on 1 bit, the confirmation mechanism usually associates an output flip-flop with each logic input, and this flip-flop is updated with the current state of the associated logic input only on condition that this input has been in this state for a minimum duration, corresponding to a duration of confirmation of this state. The output of the flip-flop therefore gives as information a confirmed state of the input, information that is used by the application.
This mechanism is illustrated in FIG. 1, which shows a logic signal S, and the output Q of the associated flip-flop, as a function of time. Initially, the signal S and the output Q of the flip-flop are both at “0”. At the time t1, the signal S switches to “1”. S remains in this state “1” until t2, when it switches back to “0”. The width of the corresponding pulse lp equals t2−t1. It is below a threshold τ, equal to the confirmation duration of the logic state “1”. The output flip-flop is not updated: the output Q remains at “0”.
At time t3, the signal S switches back to the “1” state. In the example, it remains in this state for a duration longer than the threshold τ. From the time t4, equal to t3+τ, the output flip-flop can be updated with the current state of the signal S: the output Q switches to “1”.
Therefore, with such a confirmation mechanism, the information used by the application system is not the current, instantaneous state of the logic signal S, but a confirmed state Q of this signal.
In practice, according to the prior art, the mechanism for confirming a logic signal is applied by means of a counter. Every time the value of the signal changes, the counter is reset and begins counting. Every time the counter reaches a value which corresponds to the confirmation duration, the output flip-flop is updated with the current state of the input signal. If a reverse transition occurs before the counter has reached this value, it is reset and the output flip-flop will not be updated.
An illustration of this confirmation mechanism by counting is shown in FIG. 2 for the following conditions: the two logic states “0” and “1” of the signal S are each to be confirmed and the confirmation duration is the same for both states, equal to τ. According to this mechanism, every time the state of the signal S changes, the counter is reset and counts at the speed of a clock. Every time the counter reaches a value N, which corresponds to the confirmation duration τ, the output flip-flop is updated with the current state of the signal S. At the beginning, the signal S and the output Q of the flip-flop are at “0”.
At the point A, the signal S switches from “0” to “1”; a counter CT starts counting again from zero.
At the point B, before the counter CT has reached the count N, the signal S switches from “1” to “0”: the counter CT begins counting again from zero.
At the point C, the counter reaches the threshold N: the output flip-flop is updated with the current state “0” of the signal S. In practice, the output Q remains unchanged at “0”. In the exemplary application illustrated, when the counter reaches the threshold N, it stops counting.
At the point D, the signal S switches from “0” to “1”: the counter starts counting again from zero.
At the point E, the counter reaches the threshold N: the output flip-flop is updated with the current state “1” of the signal S. In the example, the output Q switches from “0” to “1”.
This simple example shows how the short pulses, that is, shorter than the confirmation duration, are filtered by the confirmation mechanism, and also shows the delay of the item of information Q used by the application system, relative to the “true” transitions of the logic signal. This delay is substantially equal to the confirmation duration.
But in practice, depending on the application system concerned and the nature of the logic signals to be processed, the filtering requirements may vary. In particular, the confirmation durations of the two logic states of one and the same signal may vary. To illustrate this aspect, a logic signal indicating the out or in state of the landing gear of an aircraft, or a logic signal indicating the enabled or standby state of a security software process of an aircraft piloting assistance system, are examples of 1 bit logic signals for which it is useful to confirm both possible logic states, “0” and “1”, before account is taken by an application system.
More generally, each logic signal has its own specific features in terms of need for confirmation of the possible logic states, and of confirmation duration attached to each state, which is typically associated with the average frequency of appearance of this state for the signal in question, which depends on the function or on the circuit that it represents.
If consideration is given to m-bit logic signals, m≧1, it would be necessary to provide with the counting mechanism of FIG. 2 at least as many counters, with the associated logic circuitry, as signals in order to validate at least one state per signal. If several logic states are to be confirmed for each signal, for example 4, with different confirmation durations, the confirmation logic is to be multiplied by four. This solution therefore quickly becomes unsuitable when it is necessary to process a large number of logic signals and/or of logic states of these signals.
Such a confirmation mechanism, although it is simple to design, very quickly becomes cumbersome when the number of logic signals to be confirmed becomes too great.
In addition, the advances in safety of many electronic systems causes inflation in the number of logic signals to be processed, which may be greater than a hundred, whether they be signals originating from electronic sensors which are ever more numerous; or control and/or alarm signals not to mention the redundancy schemes provided in the systems which have a multiplying effect.
Other problems such as the electrical specifications of the interfaces of the system equipment add to the complexity of applying a confirmation mechanism suitable for complex electronic systems and their upgrades.